BS IEC 63011-1:2018:2019 Edition
$102.76
Integrated circuits. Three dimensional integrated circuits – Terminology
| Published By | Publication Date | Number of Pages |
| BSI | 2019 | 16 |
IEC 63011-1:2018 provides definitions pertaining to multichip integrated circuits, as vertically stacked dies using through-silicon vias (TSVs) or micro bumps. Terms and definitions related to the fabrication and test of the multichip integrated circuits are also provided.
PDF Catalog
| PDF Pages | PDF Title |
|---|---|
| 2 | undefined |
| 4 | English CONTENTS |
| 5 | FOREWORD |
| 7 | INTRODUCTION |
| 8 | 1 Scope 2 Normative reference 3 Terms and definitions 3.1 General |
| 10 | 3.2 Test method in 3D environment |
| 11 | Figure 1 – Examples of TSVs |
| 14 | Bibliography |
