{"id":79888,"date":"2024-10-17T18:38:54","date_gmt":"2024-10-17T18:38:54","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1212-1992\/"},"modified":"2024-10-24T19:41:43","modified_gmt":"2024-10-24T19:41:43","slug":"ieee-1212-1992","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1212-1992\/","title":{"rendered":"IEEE 1212 1992"},"content":{"rendered":"

New IEEE Standard – Inactive – Superseded. Superseded by IEEE Std 1212-2001 A common bus architecture (which includes functional componentsmodules, nodes, and unitsand their address space, transaction set, CSRs, and configuration information) suitable for both parallel and serial buses is provided in this standard. Bus bridges are enabled by the architecture, but their details are beyond its scope. Configuration information is self-administered by vendors and organizations based upon IEEE Registration Authority company_id.<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
15<\/td>\n1 Document Structure and Notation
1.1 Document Structure
1.2 References
1.3 Conformance Levels <\/td>\n<\/tr>\n
16<\/td>\n1.4 Technical Glossary <\/td>\n<\/tr>\n
22<\/td>\nBit Byte and Quadlet Ordering
Byte and Quadlet Ordering <\/td>\n<\/tr>\n
23<\/td>\n1.6 Numerical Values
C Code Notation
CSR ROM and Field Notation
C Expression Summary <\/td>\n<\/tr>\n
24<\/td>\nRegister Specification Format
CSR Addressing Conventions <\/td>\n<\/tr>\n
26<\/td>\nReserved Registers and Fields
Unimplemented Register (hardwired to zero) <\/td>\n<\/tr>\n
27<\/td>\n2 Objectives and Scope
2.1 Scope
2.2 Objectives <\/td>\n<\/tr>\n
29<\/td>\nTransaction Set Requirements
3.1 Transaction Overview
Read and Write Transactions
Required Transaction Types <\/td>\n<\/tr>\n
30<\/td>\nNoncoherent Lock Transactions
Optional Transaction Types <\/td>\n<\/tr>\n
31<\/td>\nSimplified Lock Model <\/td>\n<\/tr>\n
32<\/td>\n3.4 Transaction Errors
Subcommand Values for Lock4 and Lock8 <\/td>\n<\/tr>\n
33<\/td>\n3.5 Immediate Effects
Responder CSR Processing Model <\/td>\n<\/tr>\n
34<\/td>\nCSRs with Special Split-Responder Effects <\/td>\n<\/tr>\n
35<\/td>\n4 Node Addressing
4.1 Node Addresses
4.2 Extended Addressing
32-Bit Extended Addresses <\/td>\n<\/tr>\n
36<\/td>\n32-Bit Extended Addresses <\/td>\n<\/tr>\n
37<\/td>\n64-Bit Fixed Addressing
64-Bit Extended Addresses
64-Bit Extended Addresses <\/td>\n<\/tr>\n
38<\/td>\n4.4 Private Addresses
Initial Node Space
64-Bit Fixed Addressing <\/td>\n<\/tr>\n
39<\/td>\nExtended Address Spaces
Initial Node Space Components <\/td>\n<\/tr>\n
40<\/td>\n4.7 Indirect Space
Configurable Extended Addresses <\/td>\n<\/tr>\n
41<\/td>\nIndirect Space Mapping (address less than 1 Kbytes)
Indirect Space Mapping (address greater or equal to 1 Kbytes) <\/td>\n<\/tr>\n
42<\/td>\nAddress Space Offsets
ROM-Specified Offsets in the Initial Units Space
ROM-Specified Offsets in Extended Units Space <\/td>\n<\/tr>\n
44<\/td>\n5 Node Architectures
Modules Nodes and Units
Simple Single-Bus System <\/td>\n<\/tr>\n
45<\/td>\n5.2 Node States <\/td>\n<\/tr>\n
46<\/td>\nNode States
Types of Node Reset <\/td>\n<\/tr>\n
47<\/td>\n5.3 Node Testing
5.3.1 Access-Path Tests
5.3.3 Diagnostic Tests
Initialization Test Interface <\/td>\n<\/tr>\n
48<\/td>\nDiagnostic Test Interface
Disruptive Test Interface <\/td>\n<\/tr>\n
49<\/td>\nNon-Standard Diagnostic Tests
5.4 Multinode Modules
Nondisruptive Test Interface
Polled CSR Interrupt Dispatch Model <\/td>\n<\/tr>\n
50<\/td>\nMultinode Module <\/td>\n<\/tr>\n
51<\/td>\nOLR-Defective Module Removal <\/td>\n<\/tr>\n
52<\/td>\nUnit Architecture Overview
6.2.1 Interrupt-Target Registers
Synchronized Node Clocks (broadcast backplane model)
Synchronized Clocks (pipelined backplane model) <\/td>\n<\/tr>\n
53<\/td>\n6.2.2 Interrupt-Poll Registers
Synchronized Clock Registers <\/td>\n<\/tr>\n
54<\/td>\n6.3 Message Passing
Globally Synchronized Clocks
6.4.1 Clock Overview <\/td>\n<\/tr>\n
55<\/td>\n6.4.2 Clock Synchronization <\/td>\n<\/tr>\n
56<\/td>\nClock Update Models <\/td>\n<\/tr>\n
57<\/td>\nUpdating Clock Registers <\/td>\n<\/tr>\n
58<\/td>\nClock Accuracy Requirements
Memory Unit Architectures
Unit Architecture Environment <\/td>\n<\/tr>\n
60<\/td>\nCSR Definitions
Register Names and Offsets
CSR Locations <\/td>\n<\/tr>\n
62<\/td>\nCSR Access Modes <\/td>\n<\/tr>\n
63<\/td>\nSTATE-CLEAR Format
CSRs Access Modes in Nonrunning States <\/td>\n<\/tr>\n
64<\/td>\n7.2 Minimal Implementations
Unsupported Register Accesses
7.4 Register Definitions
Minimal CSR Register Set <\/td>\n<\/tr>\n
67<\/td>\nNode State Values <\/td>\n<\/tr>\n
68<\/td>\nNODE-IDS Format <\/td>\n<\/tr>\n
70<\/td>\nRESET-START Format <\/td>\n<\/tr>\n
71<\/td>\n7.4.5 INDIRECT-ADDRESS
7.4.6 INDIRECT-DATA
INDIRECT-ADDRESS Format <\/td>\n<\/tr>\n
72<\/td>\n7.4.7 SPLIT-TIMEOUT
INDIRECT-DATA Format <\/td>\n<\/tr>\n
74<\/td>\nARGUMENT Register Remote Address Format <\/td>\n<\/tr>\n
75<\/td>\nTEST-START Format
cut and tops Formats <\/td>\n<\/tr>\n
76<\/td>\nSpecial test-step values <\/td>\n<\/tr>\n
77<\/td>\n7.4.10 TEST-STATUS
Expected Interpretation of tops Values <\/td>\n<\/tr>\n
78<\/td>\nTEST-STATUS Format
test-state Format <\/td>\n<\/tr>\n
79<\/td>\nTest Status Values <\/td>\n<\/tr>\n
80<\/td>\nTest Status Values (successful and unsuccessful phase) <\/td>\n<\/tr>\n
81<\/td>\n7.4.11 UNITS-BASE
UNITS-BASE Formats
Test Status Values (active phase) <\/td>\n<\/tr>\n
82<\/td>\n7.4.12 UNITS-BOUND
UNITS-BOUND Formats <\/td>\n<\/tr>\n
83<\/td>\nExtended Space Alignment and Size <\/td>\n<\/tr>\n
85<\/td>\n7.4.14 MEMORY-BOUND
7.4.15 INTERRUPT-TARGET
MEMORY-BOUND Formats <\/td>\n<\/tr>\n
86<\/td>\n7.4.16 INTERRUPT-MASK
INTERRUPT-TARGET Format <\/td>\n<\/tr>\n
87<\/td>\n7.4.17 CLOCK-VALUE
INTERRUPT-MASK Format
CLOCK-VALUE Formats read.only) <\/td>\n<\/tr>\n
88<\/td>\n7.4.18 CLOCK-TICK-PERIOD
CLOCK-VALUE Formats (read\/write) <\/td>\n<\/tr>\n
89<\/td>\n7.4.19 CLOCK-STROBE-ARRIVED <\/td>\n<\/tr>\n
90<\/td>\nCLOCK-STROBE-ARRIVED Formats (read-only)
CLOCK-STROBE-ARRIVED Formats (read\/write) <\/td>\n<\/tr>\n
91<\/td>\n7.4.20 CLOCK-STROBE-INFO
7.4.21 Message Targets
7.4.22 ERROR-LOG Registers <\/td>\n<\/tr>\n
93<\/td>\nROM Specification
8.1 Introduction
ROM Design Assumptions
8.1.2 ROM Formats <\/td>\n<\/tr>\n
94<\/td>\nDriver and Diagnostic Identifiers
ROM Hierarchy <\/td>\n<\/tr>\n
95<\/td>\n8.1.4 ASCII Text
Software Identifier Hierarchy <\/td>\n<\/tr>\n
96<\/td>\n8.1.5 CRC Calculations <\/td>\n<\/tr>\n
97<\/td>\nCRC-16 Update Algorithm
CRC-16 Calculation Routine <\/td>\n<\/tr>\n
98<\/td>\n8.2 ROM Formats
First ROM Quadlet
Minimal ROM Format
General ROM Format
First ROM Quadlet
Minimum ROM Implementation <\/td>\n<\/tr>\n
99<\/td>\nFully Implemented CSR ROM Directory <\/td>\n<\/tr>\n
100<\/td>\n8.2.4 Directory Formats
Directory Structure
Directory Entry Format
key-type Definitions <\/td>\n<\/tr>\n
101<\/td>\nImmediate Entry Format
Offset Entry Format
Leaf or Directory Entry Format <\/td>\n<\/tr>\n
102<\/td>\nCalculating Address of Entry Value
Fetching ROM From a Desired Offset Address <\/td>\n<\/tr>\n
103<\/td>\n8.2.5 Leaf Format
8.2.6 Textual-Descriptor
Leaf Format
Textual Descriptor Locations <\/td>\n<\/tr>\n
104<\/td>\nTextual Descriptor Leaf
Minimal ASCII Textual Descriptor Leaf Format <\/td>\n<\/tr>\n
105<\/td>\n8.3 bus-info-block
Root Directory Entries
bus-info-block Format
Bus Name Example Values <\/td>\n<\/tr>\n
106<\/td>\n8.4.1 Bus-Dependent-Info
8.4.2 Module-Vendor-Id
8.4.3 Module-Hw-Version
8.4.4 Module-Spec-Id
8.4.5 Module-Sw-Version
Root Directory Entries <\/td>\n<\/tr>\n
107<\/td>\n8.4.6 Module-Dependent-Info
8.4.7 Node-Vendor-Id
8.4.8 Node-Hw-Version
8.4.9 Node-Spec-Id
8.4.10 Node-Sw-Version
8.4.11 Node-Capabilities
Node Capabilities Entry Format <\/td>\n<\/tr>\n
108<\/td>\n8.4.12 Node-Unique-Id
Unique-Id Leaf Format
Node Capabilities Bit Field Definitions <\/td>\n<\/tr>\n
109<\/td>\n8.4.1 3 Node-Units-Extent
Immediate Value Extent Entry Format
Node-Units-Extent CSR Format (offset format)
Immediate Value Units Extent Bit Field Definitions <\/td>\n<\/tr>\n
110<\/td>\n8.4.14 Node-Memory-Extent
Pointer Value Node-Units-Extent Bit Field Definitions
Extended Space Alignment and Size
Immediate Memory-Extent Entry-Field Definitions <\/td>\n<\/tr>\n
111<\/td>\nNo d e-D e p en den t-I n fo
8.4.16 Unit-Directory
Offset Memo ry-Ex ten t En try-Fie1 d Definitions <\/td>\n<\/tr>\n
112<\/td>\n8.5 Unit Directories
8.5.1 Unit-Spec-Id
8.5.2 Unit-Sw-Interface-Id
8.5.3 Unit-Dependent-Info
8.5.4 Unit-Location
Unit Directory Entries <\/td>\n<\/tr>\n
113<\/td>\n8.5.5 Unit-Poll-Mask
Unit-Locate Leaf Format
Unit-Poll Entry Format
Unit-Locate.tug Bit Field Definition <\/td>\n<\/tr>\n
114<\/td>\n8.6 Key Definitions
key-type and key-value (hexadecimal values) <\/td>\n<\/tr>\n
115<\/td>\n8.7 Company-Ids <\/td>\n<\/tr>\n
116<\/td>\n9 Bus Standard Requirements <\/td>\n<\/tr>\n
117<\/td>\n10 Bibliography <\/td>\n<\/tr>\n
119<\/td>\nA Guide for Using the CSR Architecture
A1 Bus Topologies
Al.1 Specialized Buses
Al.l.l Multiple-Bus Topologies
Central Processor\/Memory Bus
Multiple Bus Configurations <\/td>\n<\/tr>\n
120<\/td>\nAl.1.2 Dual-Port Nodes
Serial Bus Extensions
Module With Redundant Bus Connections <\/td>\n<\/tr>\n
121<\/td>\nFault Retry Protocols
A1.2
Hardware Fault Recovery
Al.2.1
Software Fault Recovery
Al.2.2
A2 System Initialization
System Initialization Summary
A2.1 <\/td>\n<\/tr>\n
122<\/td>\nNode Address Assignments
A2.2
node-id Address Assignments <\/td>\n<\/tr>\n
123<\/td>\nA2.3 Processor-Cache Model
Processor-Cache Model <\/td>\n<\/tr>\n
124<\/td>\nA2.4 Address Protection
A2.5 Power Distribution Models
TLBs Provide Selective User Protection <\/td>\n<\/tr>\n
125<\/td>\nPower Distribution Model <\/td>\n<\/tr>\n
126<\/td>\nA3 Bus Transactions
A3.1 Transaction Overview
A3.2 Transaction Components
Transaction Components <\/td>\n<\/tr>\n
127<\/td>\nRequest Subaction Fields
Response Subaction Fields <\/td>\n<\/tr>\n
128<\/td>\nA4 Bus Bridges
A4.1 Address-Invariant Mappings
CSR Byte Ordering (big-endian) <\/td>\n<\/tr>\n
129<\/td>\nA4.2 Transaction Forwarding
Bridge Byte-Line Mapping (big- and little-addressian buses) <\/td>\n<\/tr>\n
130<\/td>\nA4.3 Transaction Ordering
Split-Response Transaction Ordering
A4.3.1
A4.3.2 Buffered-Write Transparency <\/td>\n<\/tr>\n
131<\/td>\nNontransparent Request Ordering
Nontransparent Response Ordering <\/td>\n<\/tr>\n
132<\/td>\nWeakly Ordered Move Transactions
A4.3.3
A4.3.4 Queue-Dependency Deadlocks
Bridge Ordering-Shared RequestlResponse FIFOs Deadlock <\/td>\n<\/tr>\n
133<\/td>\nDeadlocked Multiprocessor Interrupts
Deadlocked Message Queues <\/td>\n<\/tr>\n
134<\/td>\nA4.4 Address Domains
Two Addressing Domains <\/td>\n<\/tr>\n
135<\/td>\nA4.5 Protection Boundaries
32\/64-Bit Bridge Mapping-Translations and Conversions <\/td>\n<\/tr>\n
136<\/td>\nA4.6 Coherence Domains
Fig A4-10 Remote Subaction Checking <\/td>\n<\/tr>\n
137<\/td>\nFig A4-11 Limited Coherence Domain <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard Control and Status Register (CSR) Architecture for Microcomputer Buses<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n1992<\/td>\n138<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":79889,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-79888","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/79888","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/79889"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=79888"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=79888"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=79888"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}