IEEE 1076-2000

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IEEE Standard VHDL Language Reference Manual

Published By	Publication Date	Number of Pages
IEEE	2000

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Description

Revision Standard – Superseded. VHSIC Hardware Description Language (VHDL) is defined. VHDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. Its primary audiences are the implementors of tools supporting the language and the advanced users of the language.

PDF Catalog

PDF Pages	PDF Title
1	Title Page
3	Introduction Participants
5	CONTENTS
11	0. Overview of this standard 0.1 Intent and scope of this standard 0.2 Structure and terminology of this standard
12	0.2.1 Syntactic description
13	0.2.2 Semantic description 0.2.3 Front matter, examples, notes, references, and annexes
15	1. Design entities and configurations 1.1 Entity declarations 1.1.1 Entity header
16	1.1.1.1 Generics
17	1.1.1.2 Ports
18	1.1.2 Entity declarative part
19	1.1.3 Entity statement part 1.2 Architecture bodies
20	1.2.1 Architecture declarative part 1.2.2 Architecture statement part
22	1.3 Configuration declarations
23	1.3.1 Block configuration
25	1.3.2 Component configuration
29	2. Subprograms and packages 2.1 Subprogram declarations
30	2.1.1 Formal parameters 2.1.1.1 Constant and variable parameters
31	2.1.1.2 Signal parameter
32	2.1.1.3 File parameters 2.2 Subprogram bodies
35	2.3 Subprogram overloading
36	2.3.1 Operator overloading 2.3.2 Signatures
37	2.4 Resolution functions
38	2.5 Package declarations
39	2.6 Package bodies
41	2.7 Conformance rules
43	3. Types
44	3.1 Scalar types 3.1.1 Enumeration types
45	3.1.1.1 Predefined enumeration types
46	3.1.2 Integer types 3.1.2.1 Predefined integer types 3.1.3 Physical types
48	3.1.3.1 Predefined physical types
49	3.1.4 Floating point types
50	3.1.4.1 Predefined floating point types 3.2 Composite types 3.2.1 Array types
52	3.2.1.1 Index constraints and discrete ranges
54	3.2.1.2 Predefined array types 3.2.2 Record types
55	3.3 Access types
56	3.3.1 Incomplete type declarations
57	3.3.2 Allocation and deallocation of objects 3.4 File types
58	3.4.1 File operations
60	3.5 Protected types 3.5.1 Protected type declarations
61	3.5.2 Protected type bodies
65	4. Declarations 4.1 Type declarations
66	4.2 Subtype declarations
67	4.3 Objects
68	4.3.1 Object declarations 4.3.1.1 Constant declarations
69	4.3.1.2 Signal declarations
70	4.3.1.3 Variable declarations
72	4.3.1.4 File declarations
73	4.3.2 Interface declarations
75	4.3.2.1 Interface lists
76	4.3.2.2 Association lists
78	4.3.3 Alias declarations
79	4.3.3.1 Object aliases
80	4.3.3.2 Nonobject aliases
81	4.4 Attribute declarations
82	4.5 Component declarations 4.6 Group template declarations
83	4.7 Group declarations
85	5. Specifications 5.1 Attribute specification
87	5.2 Configuration specification
88	5.2.1 Binding indication
90	5.2.1.1 Entity aspect
91	5.2.1.2 Generic map and port map aspects
93	5.2.2 Default binding indication
94	5.3 Disconnection specification
97	6. Names 6.1 Names
98	6.2 Simple names
99	6.3 Selected names
101	6.4 Indexed names
102	6.5 Slice names 6.6 Attribute names
105	7. Expressions 7.1 Rules for expressions
106	7.2 Operators 7.2.1 Logical operators
107	7.2.2 Relational operators
108	7.2.3 Shift operators
110	7.2.4 Adding operators
112	7.2.5 Sign operators 7.2.6 Multiplying operators
114	7.2.7 Miscellaneous operators 7.3 Operands
115	7.3.1 Literals
116	7.3.2 Aggregates 7.3.2.1 Record aggregates
117	7.3.2.2 Array aggregates
118	7.3.3 Function calls 7.3.4 Qualified expressions
119	7.3.5 Type conversions
120	7.3.6 Allocators
121	7.4 Static expressions 7.4.1 Locally static primaries
122	7.4.2 Globally static primaries
123	7.5 Universal expressions
125	8. Sequential statements 8.1 Wait statement
127	8.2 Assertion statement
128	8.3 Report statement 8.4 Signal assignment statement
130	8.4.1 Updating a projected output waveform
133	8.5 Variable assignment statement
134	8.5.1 Array variable assignments 8.6 Procedure call statement
135	8.7 If statement 8.8 Case statement
136	8.9 Loop statement
137	8.10 Next statement 8.11 Exit statement
138	8.12 Return statement 8.13 Null statement
139	9. Concurrent statements 9.1 Block statement
140	9.2 Process statement
141	9.3 Concurrent procedure call statements
142	9.4 Concurrent assertion statements
143	9.5 Concurrent signal assignment statements
145	9.5.1 Conditional signal assignments
147	9.5.2 Selected signal assignments
148	9.6 Component instantiation statements
149	9.6.1 Instantiation of a component
151	9.6.2 Instantiation of a design entity
154	9.7 Generate statements
155	10. Scope and visibility 10.1 Declarative region 10.2 Scope of declarations
156	10.3 Visibility
160	10.4 Use clauses 10.5 The context of overload resolution
163	11. Design units and their analysis 11.1 Design units 11.2 Design libraries
164	11.3 Context clauses
165	11.4 Order of analysis
167	12. Elaboration and execution 12.1 Elaboration of a design hierarchy
169	12.2 Elaboration of a block header 12.2.1 The generic clause 12.2.2 The generic map aspect 12.2.3 The port clause 12.2.4 The port map aspect
170	12.3 Elaboration of a declarative part
171	12.3.1 Elaboration of a declaration 12.3.1.1 Subprogram declarations and bodies 12.3.1.2 Type declarations
172	12.3.1.3 Subtype declarations 12.3.1.4 Object declarations
173	12.3.1.5 Alias declarations 12.3.1.6 Attribute declarations 12.3.1.7 Component declarations 12.3.2 Elaboration of a specification 12.3.2.1 Attribute specifications 12.3.2.2 Configuration specifications
174	12.3.2.3 Disconnection specifications 12.4 Elaboration of a statement part 12.4.1 Block statements 12.4.2 Generate statements
176	12.4.3 Component instantiation statements 12.4.4 Other concurrent statements
177	12.5 Dynamic elaboration 12.6 Execution of a model
178	12.6.1 Drivers 12.6.2 Propagation of signal values
181	12.6.3 Updating implicit signals
182	12.6.4 The simulation cycle
185	13. Lexical elements 13.1 Character set
188	13.2 Lexical elements, separators, and delimiters
189	13.3 Identifiers 13.3.1 Basic identifiers 13.3.2 Extended identifiers 13.4 Abstract literals
190	13.4.1 Decimal literals 13.4.2 Based literals
191	13.5 Character literals 13.6 String literals
192	13.7 Bit string literals
193	13.8 Comments
194	13.9 Reserved words
195	13.10 Allowable replacements of characters
197	14. Predefined language environment 14.1 Predefined attributes
211	14.2 Package STANDARD
218	14.3 Package TEXTIO
223	Annex A (informative) Syntax summary
243	Annex B (informative) Glossary
261	Annex C (informative) Potentially nonportable constructs
263	Annex D (informative) Bibliography