{"id":136421,"date":"2024-10-19T07:52:17","date_gmt":"2024-10-19T07:52:17","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-iso-iec-14575-2001\/"},"modified":"2024-10-25T00:02:14","modified_gmt":"2024-10-25T00:02:14","slug":"ieee-iso-iec-14575-2001","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-iso-iec-14575-2001\/","title":{"rendered":"IEEE ISO IEC 14575 2001"},"content":{"rendered":"
New IEEE Standard – Active. Enabling the construction of high-performance, scalable, modular, parallel systems with low system integration cost is discussed. Complementary use of physical connectors and cables, electrical properties, and logical protocols for point-to-point serial scalable interconnect, operating at speeds of 10200 Mb\/s and at 1 Gb\/s in copper and optic technologies, is described.<\/p>\n
PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
---|---|---|---|---|---|---|---|
1<\/td>\n | Title Page <\/td>\n<\/tr>\n | ||||||
2<\/td>\n | Copyright Page <\/td>\n<\/tr>\n | ||||||
5<\/td>\n | Introduction Participants <\/td>\n<\/tr>\n | ||||||
8<\/td>\n | CONTENTS <\/td>\n<\/tr>\n | ||||||
11<\/td>\n | 1. Overview 1.1 Scope 1.2 Purpose 2. References <\/td>\n<\/tr>\n | ||||||
13<\/td>\n | 3. Definitions 3.1 General 3.2 Glossary <\/td>\n<\/tr>\n | ||||||
16<\/td>\n | 4. Physical media and logical layers 4.1 Physical media <\/td>\n<\/tr>\n | ||||||
17<\/td>\n | 4.2 Logical layers <\/td>\n<\/tr>\n | ||||||
20<\/td>\n | 4.3 Interaction of layers <\/td>\n<\/tr>\n | ||||||
22<\/td>\n | 4.4 Implementations defined in the standard <\/td>\n<\/tr>\n | ||||||
24<\/td>\n | 5. DS-SE and DS-DE 5.1 General 5.2 DS-SE: physical medium <\/td>\n<\/tr>\n | ||||||
25<\/td>\n | 5.3 DS-SE signal level <\/td>\n<\/tr>\n | ||||||
30<\/td>\n | 5.4 DS-DE: physical medium <\/td>\n<\/tr>\n | ||||||
35<\/td>\n | 5.5 DS-DE signal level <\/td>\n<\/tr>\n | ||||||
37<\/td>\n | 5.6 DS-SE and DS-DE character level <\/td>\n<\/tr>\n | ||||||
39<\/td>\n | 5.7 DS-SE and DS-DE exchange level <\/td>\n<\/tr>\n | ||||||
42<\/td>\n | 6. TS-FO-02 fiber optic link 6.1 Physical medium <\/td>\n<\/tr>\n | ||||||
44<\/td>\n | 6.2 Signal level <\/td>\n<\/tr>\n | ||||||
46<\/td>\n | 6.3 TS-FO character level <\/td>\n<\/tr>\n | ||||||
51<\/td>\n | 7. HS-SE-10 7.1 HS-SE physical medium <\/td>\n<\/tr>\n | ||||||
55<\/td>\n | 7.2 HS-SE signal level <\/td>\n<\/tr>\n | ||||||
58<\/td>\n | 7.3 HS character level (8B\/12B code) <\/td>\n<\/tr>\n | ||||||
75<\/td>\n | 7.4 HS exchange level <\/td>\n<\/tr>\n | ||||||
83<\/td>\n | 8. HS-FO-10 fiber optic link 8.1 Physical medium <\/td>\n<\/tr>\n | ||||||
85<\/td>\n | 8.2 Signal level <\/td>\n<\/tr>\n | ||||||
87<\/td>\n | 8.3 Character level end exchange level 9. Common packet level 9.1 General discussion <\/td>\n<\/tr>\n | ||||||
88<\/td>\n | 9.2 Packet format <\/td>\n<\/tr>\n | ||||||
89<\/td>\n | 9.3 Networks and routing 9.4 Error detection, recovery, and reporting 10. Conformance criteria 10.1 Conformance statements 10.2 Definition of subsets <\/td>\n<\/tr>\n | ||||||
90<\/td>\n | 10.3 Conformance statements and cable markings <\/td>\n<\/tr>\n | ||||||
91<\/td>\n | Annex A (Normative) DS-DE connector specification <\/td>\n<\/tr>\n | ||||||
98<\/td>\n | Annex B (Normative) HS-SE connector specification <\/td>\n<\/tr>\n | ||||||
103<\/td>\n | Annex C (Normative) TS-FO and HS-FO connector specifications <\/td>\n<\/tr>\n | ||||||
117<\/td>\n | Annex D (Informative) Rationale <\/td>\n<\/tr>\n | ||||||
121<\/td>\n | Annex E (Informative) Switch chips, switches, and fabrics <\/td>\n<\/tr>\n | ||||||
122<\/td>\n | Annex F (Informative) Use of the transaction layer\u2014Asynchronous transfer mode (ATM) example <\/td>\n<\/tr>\n | ||||||
131<\/td>\n | Annex G (Informative) Error handling <\/td>\n<\/tr>\n | ||||||
132<\/td>\n | Annex H (Informative) Flow control calculations <\/td>\n<\/tr>\n | ||||||
134<\/td>\n | Annex I (Informative) Synchronized channel communications <\/td>\n<\/tr>\n | ||||||
137<\/td>\n | Annex J (Informative) Example DS-SE driver circuit <\/td>\n<\/tr>\n | ||||||
139<\/td>\n | Annex K (Informative) DS-DE optional power supply recommendation <\/td>\n<\/tr>\n | ||||||
140<\/td>\n | Annex L (Informative) DS-DE fixed connector PCB recommendation <\/td>\n<\/tr>\n | ||||||
141<\/td>\n | Annex M (Informative) DS-DE cable (10 core) recommendation <\/td>\n<\/tr>\n | ||||||
142<\/td>\n | Annex N (Informative) DS-DE multiway connector housing recommendation <\/td>\n<\/tr>\n | ||||||
143<\/td>\n | Annex O (Informative) HS-SE fixed connector PCB recommendation <\/td>\n<\/tr>\n | ||||||
144<\/td>\n | Annex P (Informative) HS-SE cable recommendation <\/td>\n<\/tr>\n | ||||||
145<\/td>\n | Annex Q (Informative) HS-SE connector multiway housing recommendation <\/td>\n<\/tr>\n | ||||||
146<\/td>\n | Annex R (Informative)TS\/HS-FO connector PCB and front panel cut-out recommendation <\/td>\n<\/tr>\n | ||||||
147<\/td>\n | Annex S (Informative) TS\/HS-FO fiber cable recommendation <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" ISO\/IEC 14575:2000 (IEEE Std 1355-1995) Information Technology — Microprocessor systems — Heterogeneous InterConnect (HIC) (Low-Cost, Low-Latency Scalable Serial Interconnect for Parallel System Construction)<\/b><\/p>\n |