{"id":146944,"date":"2024-10-19T08:37:23","date_gmt":"2024-10-19T08:37:23","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-iso-iec-10861-1994\/"},"modified":"2024-10-25T00:53:39","modified_gmt":"2024-10-25T00:53:39","slug":"ieee-iso-iec-10861-1994","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-iso-iec-10861-1994\/","title":{"rendered":"IEEE ISO IEC 10861 1994"},"content":{"rendered":"
New IEEE Standard – Active. The operation, functions, and attributes of a parallel system bus (PSB), called MULTIBUS II, are defined. A high-performance backplane bus intended for use in multiple processor systems, the PSB incorporates synchronous, 32-bit multiplexed address\/data, with error detection, and uses a 10 MHz bus clock. This design is intended to provide reliable state-of-the-art operation and to allow the implementation of cost-effective, high-performance VLSI for the bus interface. Memory, I\/O, message, and geographic address spaces are defined. Error detection and retry are provided for messages. The message-passing design allows a VLSI implementation, so that virtually all modules on the bus will utilize the bus at its highest performance32 to 40 Mbyte\/s. An overview of PSB, signal descriptions, the PSB protocol, electrical characteristics, and mechanical specifications are covered.<\/p>\n
PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
---|---|---|---|---|---|---|---|
1<\/td>\n | Title Page <\/td>\n<\/tr>\n | ||||||
5<\/td>\n | Introduction <\/td>\n<\/tr>\n | ||||||
6<\/td>\n | Participants <\/td>\n<\/tr>\n | ||||||
8<\/td>\n | CONTENTS <\/td>\n<\/tr>\n | ||||||
11<\/td>\n | 1. General overview 1.1 Scope 1.2 Normative references <\/td>\n<\/tr>\n | ||||||
12<\/td>\n | 2. Definitions <\/td>\n<\/tr>\n | ||||||
15<\/td>\n | 3. Guide to notation 3.1 General 3.2 Signal notation 3.3 Figure notation <\/td>\n<\/tr>\n | ||||||
16<\/td>\n | 3.4 Notation in state-flow diagrams 3.5 Notation for multiple bit data representation <\/td>\n<\/tr>\n | ||||||
17<\/td>\n | 4. PSB overview 4.1 General <\/td>\n<\/tr>\n | ||||||
18<\/td>\n | 4.2 Address\/data path and system control signals 4.3 Message-passing facility 4.4 Interconnect facility 4.5 Synchronous operation of the PSB 4.6 Bus operations on the PSB <\/td>\n<\/tr>\n | ||||||
22<\/td>\n | 4.7 Central services module 5. Signal descriptions 5.1 General 5.2 Signal groups <\/td>\n<\/tr>\n | ||||||
30<\/td>\n | 6. PSB protocol 6.1 General <\/td>\n<\/tr>\n | ||||||
31<\/td>\n | 6.2 Arbitration operation <\/td>\n<\/tr>\n | ||||||
41<\/td>\n | 6.3 Transfer operation <\/td>\n<\/tr>\n | ||||||
62<\/td>\n | 6.4 Exception operation <\/td>\n<\/tr>\n | ||||||
66<\/td>\n | 6.5 Central control functions <\/td>\n<\/tr>\n | ||||||
73<\/td>\n | 6.6 State-flow diagrams <\/td>\n<\/tr>\n | ||||||
86<\/td>\n | 7. Electrical characteristics 7.1 General <\/td>\n<\/tr>\n | ||||||
87<\/td>\n | 7.2 AC timing specifications <\/td>\n<\/tr>\n | ||||||
94<\/td>\n | 7.3 DC specifications for signals <\/td>\n<\/tr>\n | ||||||
95<\/td>\n | 7.4 Current limitations per connector <\/td>\n<\/tr>\n | ||||||
96<\/td>\n | 7.5 Pin assignments <\/td>\n<\/tr>\n | ||||||
99<\/td>\n | 8. Mechanical specifications 8.1 General <\/td>\n<\/tr>\n | ||||||
100<\/td>\n | 8.2 Board sizes and dimensions <\/td>\n<\/tr>\n | ||||||
101<\/td>\n | 8.3 Printed board layout considerations 8.4 Front panel 8.5 Connectors <\/td>\n<\/tr>\n | ||||||
102<\/td>\n | 8.6 Backplanes <\/td>\n<\/tr>\n | ||||||
110<\/td>\n | 9. IEEE 1296 System Interface specification 9.1 Overview <\/td>\n<\/tr>\n | ||||||
111<\/td>\n | 9.2 Interconnect space operation <\/td>\n<\/tr>\n | ||||||
126<\/td>\n | 9.3 I\/O space operation <\/td>\n<\/tr>\n | ||||||
127<\/td>\n | 9.4 Memory space operations 9.5 Message space operations <\/td>\n<\/tr>\n | ||||||
138<\/td>\n | 10. IEEE 1296 capabilities 10.1 Characteristic codes <\/td>\n<\/tr>\n | ||||||
139<\/td>\n | Annex A\u2014Recommended documentation practices <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" ISO\/IEC Standard for Information Technology- Microprocessor Systems- High-Performance Synchronous 32-Bit Bus: Multibus II<\/b><\/p>\n |