{"id":226195,"date":"2024-10-19T14:42:02","date_gmt":"2024-10-19T14:42:02","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/bs-en-62386-1012014\/"},"modified":"2024-10-25T08:36:57","modified_gmt":"2024-10-25T08:36:57","slug":"bs-en-62386-1012014","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/bsi\/bs-en-62386-1012014\/","title":{"rendered":"BS EN 62386-101:2014"},"content":{"rendered":"

IEC 62386-101:2014 is applicable to system components in a bus system for control by digital signals of electronic lighting equipment. This electronic lighting equipment should be in line with the requirements of IEC 61347, with the addition of d.c. supplies. This second edition cancels and replaces the first edition published in 2009. This edition constitutes a technical revision. This edition includes the following significant technical changes with respect to the previous edition: a) collection of all bus timing requirements defined in IEC 62386-101:2009 and IEC 62386-102:2009 and rework of the timing requirements to facilitate the preparation of a future control devices standard, taking particular account of the requirements for multi-master systems. The 10 % tolerances have been replaced by minimum and maximum timing values; b) integration of multi-master timing requirements; c) extension of the defined forward frames; d) addition of wiring requirements; e) improvement of the bus power supply requirements; f) improvement of test sequences and description of the test sequences in the form of pseudo code instead of flow charts. This publication is to be read in conjunction with \/2.<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
6<\/td>\nEnglish
CONTENTS <\/td>\n<\/tr>\n
11<\/td>\nINTRODUCTION
Figures
Figure 1 \u2013 IEC 62386 graphical overview <\/td>\n<\/tr>\n
12<\/td>\n1 Scope
2 Normative references
3 Terms and definitions <\/td>\n<\/tr>\n
17<\/td>\n4 General
4.1 Purpose
4.2 Version number
4.3 System structure and architecture
Tables
Table 1 \u2013 System components <\/td>\n<\/tr>\n
18<\/td>\n4.4 System information flow
4.5 Command types
Figure 2 \u2013 System structure example
Figure 3 \u2013 Communication between bus units (example) <\/td>\n<\/tr>\n
19<\/td>\n4.6 Bus units
4.6.1 Transmitters and receivers in bus units
4.6.2 Control gear
4.6.3 Input device
4.6.4 Single master application controller
Table 2 \u2013 Transmitters and receivers in bus units <\/td>\n<\/tr>\n
20<\/td>\n4.6.5 Multi-master application controller
4.6.6 Sharing an interface
Figure 4 \u2013 Example of a shared interface <\/td>\n<\/tr>\n
21<\/td>\n4.7 Bus power supply and load calculations
4.7.1 Current demand coverage
4.7.2 Maximum signal current compliance
4.7.3 Simplified system calculation
4.8 Wiring
4.8.1 Wiring structure
4.8.2 Wiring specification <\/td>\n<\/tr>\n
22<\/td>\n4.9 Insulation
4.10 Earthing of the bus
4.11 Power interruptions at bus units
4.11.1 Different levels of power interruptions
4.11.2 Short power interruptions of external power supply
Table 3 \u2013 Power-interruption timing of external power
Table 4 \u2013 Power-interruption timing of bus power <\/td>\n<\/tr>\n
23<\/td>\n4.11.3 External power cycle
4.11.4 Short interruptions of bus power supply
4.11.5 Bus power down
4.11.6 System start-up timing
Table 5 \u2013 Short power interruptions <\/td>\n<\/tr>\n
24<\/td>\nFigure 5 \u2013 Start up timing example
Table 6 \u2013 Start-up timing <\/td>\n<\/tr>\n
25<\/td>\n5 Electrical specification
5.1 General
5.2 Marking of the interface
5.3 Capacitors between the interface and earth
5.4 Signal voltage rating
Table 7 \u2013 System voltage levels
Table 8 \u2013 Receiver voltage levels <\/td>\n<\/tr>\n
26<\/td>\n5.5 Signal current rating
5.6 Marking of bus powered bus unit
5.7 Signal rise time and fall time
Table 9 \u2013 Transmitter voltage levels
Table 10 \u2013 Current rating <\/td>\n<\/tr>\n
27<\/td>\nFigure 6 \u2013 Maximum signal rise and fall time measurements
Figure 7 \u2013 Minimum signal rise and fall time measurements
Table 11 \u2013 Signal rise and fall times <\/td>\n<\/tr>\n
28<\/td>\n6 Bus power supply
6.1 General
6.2 Marking of the bus power supply terminals
6.3 Capacitors between the interface and earth
6.4 Voltage rating
6.5 Current rating
6.5.1 General current rating
Table 12 \u2013 Bus power supply output voltage <\/td>\n<\/tr>\n
29<\/td>\n6.5.2 Single bus power supply current rating
6.5.3 Integrated bus power supply current rating
6.5.4 Dynamic behaviour of the bus power supply
Table 13 \u2013 Bus power supply current rating
Table 14 \u2013 Bus power supply dynamic behaviour <\/td>\n<\/tr>\n
30<\/td>\n6.6 Bus power supply timing requirements
6.6.1 Short power supply interruptions
Figure 8 \u2013 Bus power supply current behaviour
Figure 9 \u2013 Bus power supply voltage behaviour <\/td>\n<\/tr>\n
31<\/td>\n6.6.2 Short circuit behaviour
7 Transmission protocol structure
7.1 General
7.2 Bit encoding
7.2.1 Start bit and data bit encoding
Figure 10 \u2013 Frame example
Table 15 \u2013 Short circuit timing behaviour <\/td>\n<\/tr>\n
32<\/td>\n7.2.2 Stop condition encoding
7.3 Frame description
7.4 Frame types
7.4.1 16\u00a0bit forward frame
7.4.2 24\u00a0bit forward frame
7.4.3 Reserved forward frame
7.4.4 Backward frame
7.4.5 Proprietary forward frames
Figure 11 \u2013 Bi-phase encoded bits <\/td>\n<\/tr>\n
33<\/td>\n8 Timing
8.1 Transmitter timing
8.1.1 Transmitter bit timing
Figure 12 \u2013 Bit timing example <\/td>\n<\/tr>\n
34<\/td>\n8.1.2 Transmitter frame sequence timing
8.2 Receiver timing
8.2.1 Receiver bit timing
Figure 13 \u2013 Settling time illustration
Table 16 \u2013 Transmitter bit timing
Table 17 \u2013 Transmitter settling time values <\/td>\n<\/tr>\n
35<\/td>\nTable 18 \u2013 Receiver timing starting at the beginning of a logical bit
Table 19 \u2013 Receiver timing starting at an edge inside of a logical bit <\/td>\n<\/tr>\n
36<\/td>\n8.2.2 Receiver bit timing violation
8.2.3 Receiver frame size violation
8.2.4 Receiver frame sequence timing
Figure 14 \u2013 Receiver timing decision example <\/td>\n<\/tr>\n
37<\/td>\n8.2.5 Reception of backward frames
8.3 Multi-master transmitter timing
8.3.1 Multi-master transmitter bit timing
Table 20 \u2013 Receiver settling time values
Table 21 \u2013 Multi-master transmitter bit timing <\/td>\n<\/tr>\n
38<\/td>\n8.3.2 Multi-master transmitter frame sequence timing
9 Method of operation
9.1 Collision avoidance, collision detection and collision recovery
9.1.1 General
Table 22 \u2013 Multi-master transmitter settling time values <\/td>\n<\/tr>\n
39<\/td>\n9.1.2 Collision avoidance
9.1.3 Collision detection
Table 23 \u2013 Checking a logical bit, starting at an edge at the beginning of the bit <\/td>\n<\/tr>\n
40<\/td>\n9.1.4 Collision recovery
Figure 15 \u2013 Collision detection timing decision example
Table 24 \u2013 Checking a logical bit, starting at an edge inside the bit <\/td>\n<\/tr>\n
41<\/td>\n9.2 Transactions
Figure 16 \u2013 Collision recovery example
Table 25 \u2013 Collision recovery timing <\/td>\n<\/tr>\n
42<\/td>\n9.3 Send-twice forward frames and send-twice commands
9.4 Command iteration <\/td>\n<\/tr>\n
43<\/td>\n9.5 Usage of a shared interface
9.5.1 General
9.5.2 Backward frames
9.5.3 Forward frames
9.6 Use of multiple bus power supplies
Table 26 \u2013 Transmitter command iteration timing
Table 27 \u2013 Receiver command iteration timing <\/td>\n<\/tr>\n
44<\/td>\n9.7 Command execution
10 Declaration of variables
11 Definition of commands
12 Test procedures
12.1 General notes on test
12.1.1 Abbreviations
12.1.2 Ambient temperature <\/td>\n<\/tr>\n
45<\/td>\n12.1.3 External power supply voltage and frequency
12.1.4 Measurement requirements
12.1.5 Test signal generators and bus voltage sources
12.1.6 Deviation from documentation
12.1.7 Test setup
12.1.8 Notation <\/td>\n<\/tr>\n
46<\/td>\nTable 28 \u2013 Function call keywords <\/td>\n<\/tr>\n
49<\/td>\nTable 29 \u2013 Defined operators <\/td>\n<\/tr>\n
51<\/td>\n12.2 General interface tests
12.2.1 Label and literature check
12.2.2 Interface marking check <\/td>\n<\/tr>\n
52<\/td>\n12.2.3 Bus powered bus unit marking check <\/td>\n<\/tr>\n
54<\/td>\n12.2.4 Bus power supply marking check <\/td>\n<\/tr>\n
56<\/td>\n12.2.5 Insulation test <\/td>\n<\/tr>\n
57<\/td>\n12.2.6 Capacitor check
12.3 Bus power supply tests
12.3.1 Voltage rating test <\/td>\n<\/tr>\n
58<\/td>\n12.3.2 Voltage rise time test
12.3.3 Current rating test <\/td>\n<\/tr>\n
59<\/td>\nFigure 17 \u2013 Current rating test signal <\/td>\n<\/tr>\n
60<\/td>\n12.3.4 Dynamic behaviour test
Figure 18 \u2013 Dynamic behaviour test setup <\/td>\n<\/tr>\n
61<\/td>\nFigure 19 \u2013 Dynamic behaviour test signal <\/td>\n<\/tr>\n
62<\/td>\n12.3.5 Power-on open circuit test <\/td>\n<\/tr>\n
63<\/td>\n12.3.6 Power-on timing test <\/td>\n<\/tr>\n
64<\/td>\n12.3.7 Power supply short interruptions test <\/td>\n<\/tr>\n
65<\/td>\n12.3.8 Power supply short circuit test <\/td>\n<\/tr>\n
66<\/td>\n12.3.9 Power supply current consumption test <\/td>\n<\/tr>\n
67<\/td>\n12.4 Control device tests
12.5 Control gear tests <\/td>\n<\/tr>\n
68<\/td>\nAnnex A (informative) Background information for systems
A.1 Wiring information <\/td>\n<\/tr>\n
69<\/td>\nA.2 System architectures
A.2.1 General
A.2.2 Single master architecture
Table A.1 \u2013 Maximum cable length <\/td>\n<\/tr>\n
70<\/td>\nA.2.3 Multi-master architecture with one application controller
Figure A.1 \u2013 Single master architecture example <\/td>\n<\/tr>\n
71<\/td>\nA.2.4 Multi-master architecture with more than one application controller
Figure A.2 \u2013 Multi-master architecture example with one application controller <\/td>\n<\/tr>\n
72<\/td>\nA.2.5 Multi-master architecture with integrated input device
Figure A.3 \u2013 Multi-master architecture example with two application controllers <\/td>\n<\/tr>\n
73<\/td>\nA.2.6 Multi-master architecture with integrated input device and power supply
Figure A.4 \u2013 Multi-master architecture example with integrated input device <\/td>\n<\/tr>\n
74<\/td>\nA.3 Collision detection
Figure A.5 \u2013 Multi-master architecture example with integrate input device and bus power supply <\/td>\n<\/tr>\n
75<\/td>\nA.4 Timing definition explanations
A.4.1 General
A.4.2 Receiver timing
A.4.3 Transmitter timing
Figure A.6 \u2013 Collision detection timing diagram <\/td>\n<\/tr>\n
76<\/td>\nA.4.4 Grey areas
A.5 Maximum current consumption calculation explanation
A.5.1 Single bus power supply
Figure A.7 \u2013 Transmitter and receiver timing illustration <\/td>\n<\/tr>\n
77<\/td>\nA.5.2 Multiple bus power supplies
Figure A.8 \u2013 Bus power supply current values
Figure A.9 \u2013 Current demand coverage <\/td>\n<\/tr>\n
78<\/td>\nA.5.3 Redundant bus power supplies
Figure A.10 \u2013 Combination of 4 bus power supplies
Figure A.11 \u2013 Redundant bus power supplies <\/td>\n<\/tr>\n
79<\/td>\nA.6 Communication layer overview
A.6.1 General
A.6.2 Physical layer
A.6.3 Data link layer
A.6.4 Network layer
Table A.2 \u2013 OSI layer model of IEC\u00a062386 <\/td>\n<\/tr>\n
80<\/td>\nA.6.5 Transport layer
A.6.6 Session layer
A.6.7 Presentation layer
A.6.8 Application layer <\/td>\n<\/tr>\n
81<\/td>\nBibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

Digital addressable lighting interface – General requirements. System components<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
BSI<\/b><\/a><\/td>\n2015<\/td>\n84<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":226198,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[525,2641],"product_tag":[],"class_list":{"0":"post-226195","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-29-140-50","7":"product_cat-bsi","9":"first","10":"instock","11":"sold-individually","12":"shipping-taxable","13":"purchasable","14":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/226195","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/226198"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=226195"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=226195"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=226195"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}