{"id":399615,"date":"2024-10-20T04:44:01","date_gmt":"2024-10-20T04:44:01","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1149-7-2009\/"},"modified":"2024-10-26T08:32:18","modified_gmt":"2024-10-26T08:32:18","slug":"ieee-1149-7-2009","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1149-7-2009\/","title":{"rendered":"IEEE 1149.7-2009"},"content":{"rendered":"

New IEEE Standard – Active. This specification describes circuitry that may be added to an integrated circuit to provide access to on-chip Test Access Ports (TAPs) specified by IEEE Std 1149.1TM-2001. The circuitry uses IEEE 1149.1-2001 as its foundation, providing complete backward compatibility, while aggressively adding features to support test and applications debug. It defines six classes of 1149.7 Test Access Ports (TAP.7s), T0\u2013T5, with each class providing incremental capability, building on that of the lower level classes. Class T0 provides the behavior specified by 1149.1 from startup when there are multiple on-chip TAPs. Class T1 adds common debug functions and features to minimize power consumption. Class T2 adds operating modes that maximize scan performance. It also provides an optional hot-connection capability to prevent system corruption when a connection is made to a powered system. Class T3 supports operation in either a fourwire Series or Star Scan Topology. Class T4 provides for communication with either a two-pin or four-pin interface. The two-pin operation serializes 1149.1 transactions and provides for higher Test Clock rates. Class T5 adds the ability to perform data transfers concurrent with scan, supports utilization of functions other than scan, and provides control of TAP.7 pins to custom debug technologies in a manner that ensures current and future interoperability.<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
1<\/td>\nIEEE Std 1149.7-2009 Front Cover <\/td>\n<\/tr>\n
3<\/td>\nTitle Page <\/td>\n<\/tr>\n
6<\/td>\nIntroduction
Notice to users
Laws and regulations <\/td>\n<\/tr>\n
7<\/td>\nCopyrights
Updating of IEEE documents
Errata
Interpretations
Patents <\/td>\n<\/tr>\n
8<\/td>\nParticipants <\/td>\n<\/tr>\n
9<\/td>\nContents <\/td>\n<\/tr>\n
36<\/td>\nFigures <\/td>\n<\/tr>\n
47<\/td>\nTables <\/td>\n<\/tr>\n
53<\/td>\nImportant Notice
1. Overview
1.1 Scope
1.2 Purpose <\/td>\n<\/tr>\n
54<\/td>\n1.3 Contrasting IEEE Std 1149.1-2001 and this standard <\/td>\n<\/tr>\n
55<\/td>\n1.4 Challenges <\/td>\n<\/tr>\n
56<\/td>\n1.5 Important considerations
1.6 Nomenclature <\/td>\n<\/tr>\n
58<\/td>\n1.7 Ensuring transparency to IEEE 1149.1 intellectual property <\/td>\n<\/tr>\n
59<\/td>\n1.8 Maximizing compatibility with 1149.1 IP <\/td>\n<\/tr>\n
62<\/td>\n1.9 Scalability <\/td>\n<\/tr>\n
64<\/td>\n1.10 Flexibility <\/td>\n<\/tr>\n
66<\/td>\n1.11 Document content <\/td>\n<\/tr>\n
67<\/td>\n1.12 Document organization <\/td>\n<\/tr>\n
71<\/td>\n1.13 Using the standard <\/td>\n<\/tr>\n
72<\/td>\n1.14 Conventions <\/td>\n<\/tr>\n
78<\/td>\n2. Normative references <\/td>\n<\/tr>\n
79<\/td>\n3. Definitions, acronyms, and abbreviations
3.1 Definitions <\/td>\n<\/tr>\n
83<\/td>\n3.2 Acronyms and abbreviations <\/td>\n<\/tr>\n
88<\/td>\n4. TAP.7 concepts and architecture
4.1 Introduction
4.2 Concepts supporting system architecture <\/td>\n<\/tr>\n
103<\/td>\n4.3 Concepts supporting pin efficiency <\/td>\n<\/tr>\n
111<\/td>\n4.4 Concepts supporting capability <\/td>\n<\/tr>\n
112<\/td>\n4.5 IEEE 1149.7 architecture <\/td>\n<\/tr>\n
117<\/td>\n4.6 Operating models <\/td>\n<\/tr>\n
120<\/td>\n5. T0\u2013T3 TAP.7 operational overview
5.1 Introduction
5.2 T0 TAP.7 <\/td>\n<\/tr>\n
124<\/td>\n5.3 T1 TAP.7 <\/td>\n<\/tr>\n
134<\/td>\n5.4 T2 TAP.7 <\/td>\n<\/tr>\n
141<\/td>\n5.5 T3 TAP.7 <\/td>\n<\/tr>\n
153<\/td>\n6. T4\u2013T5 TAP.7 operational overview
6.1 Introduction <\/td>\n<\/tr>\n
154<\/td>\n6.2 T4 TAP.7 <\/td>\n<\/tr>\n
163<\/td>\n6.3 T5 TAP.7 <\/td>\n<\/tr>\n
172<\/td>\n6.4 TAP.7 feature summary <\/td>\n<\/tr>\n
174<\/td>\n7. System concepts
7.1 Introduction
7.2 Key system attributes
7.3 DTS\/TS connectivity with a mix of technologies <\/td>\n<\/tr>\n
176<\/td>\n7.4 TAP.7 deployment scenarios <\/td>\n<\/tr>\n
177<\/td>\n7.5 Chip TAPC hierarchy <\/td>\n<\/tr>\n
178<\/td>\n7.6 Combined view of TAP connectivity and TAPC hierarchy <\/td>\n<\/tr>\n
179<\/td>\n7.7 Chips, components, and boards <\/td>\n<\/tr>\n
181<\/td>\n8. TAPC hierarchy
8.1 Introduction
8.2 Selection\/deselection with the TAPC hierarchy <\/td>\n<\/tr>\n
182<\/td>\n8.3 TAPC selection\/deselection characteristics <\/td>\n<\/tr>\n
184<\/td>\n8.4 ADTAPC selection\/deselection <\/td>\n<\/tr>\n
186<\/td>\n8.5 CLTAPC selection\/deselection <\/td>\n<\/tr>\n
188<\/td>\n8.6 EMTAPC selection\/deselection <\/td>\n<\/tr>\n
189<\/td>\n8.7 Using a common selection\/deselection protocol across technologies
8.8 RSU deployment <\/td>\n<\/tr>\n
190<\/td>\n8.9 Using the TAPC hierarchy <\/td>\n<\/tr>\n
191<\/td>\n8.10 Test\/debug applications and the TAPC hierarchy <\/td>\n<\/tr>\n
194<\/td>\n9. Registers, commands, and scan paths
9.1 Introduction
9.2 Command basics <\/td>\n<\/tr>\n
196<\/td>\n9.3 Register portfolio <\/td>\n<\/tr>\n
199<\/td>\n9.4 Command portfolio <\/td>\n<\/tr>\n
206<\/td>\n9.5 Representation of commands in examples
9.6 Global and Local Register programming with commands <\/td>\n<\/tr>\n
207<\/td>\n9.7 1Scan paths <\/td>\n<\/tr>\n
218<\/td>\n9.8 Two-part commands
9.9 Three-part commands <\/td>\n<\/tr>\n
222<\/td>\n9.10 RDBACKx and CNFGx Registers <\/td>\n<\/tr>\n
228<\/td>\n9.11 An approach to implementing command processing and scan paths <\/td>\n<\/tr>\n
232<\/td>\n10. RSU ancillary services
10.1 Introduction
10.2 Resets <\/td>\n<\/tr>\n
239<\/td>\n10.3 Start-up options <\/td>\n<\/tr>\n
247<\/td>\n10.4 Escape Detection <\/td>\n<\/tr>\n
253<\/td>\n10.5 Selection Alert <\/td>\n<\/tr>\n
259<\/td>\n10.6 Deselection Alert <\/td>\n<\/tr>\n
260<\/td>\n10.7 Programming considerations <\/td>\n<\/tr>\n
261<\/td>\n10.8 ADTAPC State Machine <\/td>\n<\/tr>\n
263<\/td>\n11. RSU Online\/Offline capability
11.1 Introduction
11.2 Managing Online\/Offline operation <\/td>\n<\/tr>\n
264<\/td>\n11.3 Online\/Offline operating principles <\/td>\n<\/tr>\n
267<\/td>\n11.4 Initiating Offline operation <\/td>\n<\/tr>\n
269<\/td>\n11.5 Initiating Online operation <\/td>\n<\/tr>\n
270<\/td>\n11.6 Context-sensitive response to Selection and Deselection Escapes <\/td>\n<\/tr>\n
273<\/td>\n11.7 Selection Sequence <\/td>\n<\/tr>\n
284<\/td>\n11.8 Parking-state considerations <\/td>\n<\/tr>\n
287<\/td>\n11.9 Control State Machine <\/td>\n<\/tr>\n
310<\/td>\n11.10 Programming considerations <\/td>\n<\/tr>\n
314<\/td>\n12. TAP signals
12.1 Introduction
12.2 TAP.7 Class\/signal relationships <\/td>\n<\/tr>\n
316<\/td>\n12.3 Signal function and bias <\/td>\n<\/tr>\n
318<\/td>\n12.4 Test Reset (nTRST and nTRST_PD) signals <\/td>\n<\/tr>\n
319<\/td>\n12.5 TAP.7 signal functions with corresponding IEEE 1149.1 names
12.6 Test Clock (TCK) <\/td>\n<\/tr>\n
320<\/td>\n12.7 Test Mode Select (TMS\/TMSC) <\/td>\n<\/tr>\n
327<\/td>\n12.8 Test Data Input (TDI\/TDIC) <\/td>\n<\/tr>\n
330<\/td>\n12.9 Test Data Output (TDO\/TDOC) <\/td>\n<\/tr>\n
332<\/td>\n12.10 Offline-at-Start-up behavior <\/td>\n<\/tr>\n
333<\/td>\n12.11 TAP connections <\/td>\n<\/tr>\n
334<\/td>\n12.12 Applicability of this standard <\/td>\n<\/tr>\n
335<\/td>\n12.13 Recommendations for interoperability <\/td>\n<\/tr>\n
338<\/td>\n13. TDO(C) Signal Drive Policy
13.1 Introduction
13.2 TDO(C) Signal Drive Types <\/td>\n<\/tr>\n
340<\/td>\n13.3 Factors affecting the TDO(C) Drive Policy <\/td>\n<\/tr>\n
341<\/td>\n13.4 TDO(C) Drive Policy template <\/td>\n<\/tr>\n
348<\/td>\n13.5 T0 TAP.7 TDOC Drive Policy <\/td>\n<\/tr>\n
349<\/td>\n13.6 T1 and T2 TAP.7 TDOC Drive Policy <\/td>\n<\/tr>\n
351<\/td>\n13.7 T3 and above TAP.7 TDOC Drive Policy <\/td>\n<\/tr>\n
354<\/td>\n13.8 STL Group Membership <\/td>\n<\/tr>\n
368<\/td>\n13.9 EPU Group Membership <\/td>\n<\/tr>\n
372<\/td>\n13.10 Drive Policy summary <\/td>\n<\/tr>\n
373<\/td>\n13.11 An approach to implementing TDOC Drive Policy <\/td>\n<\/tr>\n
376<\/td>\n13.12 Programming considerations <\/td>\n<\/tr>\n
377<\/td>\n14. TMS(C) Signal Drive Policy
14.1 Introduction
14.2 TMS(C) output bit types <\/td>\n<\/tr>\n
380<\/td>\n14.3 Drive policy by output bit type <\/td>\n<\/tr>\n
381<\/td>\n14.4 TMSC Signal Drive Types <\/td>\n<\/tr>\n
383<\/td>\n14.5 Dormant Bit Drive Policy
14.6 Precharge Bit Drive Policy <\/td>\n<\/tr>\n
384<\/td>\n14.7 RDY Bit Drive Policy <\/td>\n<\/tr>\n
387<\/td>\n14.8 TDO Bit Drive Policy <\/td>\n<\/tr>\n
391<\/td>\n14.9 Transport Bit Drive Policy <\/td>\n<\/tr>\n
392<\/td>\n14.10 An approach to implementing TMSC Drive Policy <\/td>\n<\/tr>\n
396<\/td>\n14.11 Programming considerations <\/td>\n<\/tr>\n
398<\/td>\n15. IEEE 1149.1-compliance concepts
15.1 Introduction
15.2 Background <\/td>\n<\/tr>\n
399<\/td>\n15.3 Test and debug views of a system of interest <\/td>\n<\/tr>\n
400<\/td>\n15.4 An approach to implementing EMTAPC selection\/deselection <\/td>\n<\/tr>\n
401<\/td>\n16. T0 TAP.7
16.1 Introduction
16.2 Deployment <\/td>\n<\/tr>\n
402<\/td>\n16.3 Capabilities
16.4 Configurations <\/td>\n<\/tr>\n
403<\/td>\n16.5 Start-up behavior
16.6 Supporting multiple on-chip TAPCs <\/td>\n<\/tr>\n
404<\/td>\n16.7 Controlling the selection state of EMTAPCs <\/td>\n<\/tr>\n
407<\/td>\n16.8 Control via the CLTAPC Instruction Register <\/td>\n<\/tr>\n
411<\/td>\n16.9 Control via one or more CLTAPC Data Registers <\/td>\n<\/tr>\n
413<\/td>\n16.10 Control via internal or external tapc_select signals <\/td>\n<\/tr>\n
415<\/td>\n16.11 Example use cases <\/td>\n<\/tr>\n
418<\/td>\n16.12 Identification of on-chip TAP controller(s) <\/td>\n<\/tr>\n
419<\/td>\n16.13 Multiple dies in one package <\/td>\n<\/tr>\n
424<\/td>\n16.14 Managing STL Group Membership
16.15 RSU operation <\/td>\n<\/tr>\n
425<\/td>\n16.16 Programming considerations <\/td>\n<\/tr>\n
426<\/td>\n17. Extended concepts
17.1 Introduction
17.2 Suitability of BYPASS and IDCODE instructions for extended control
17.3 ZBS detection <\/td>\n<\/tr>\n
427<\/td>\n17.4 Incrementing, locking, and clearing the ZBS count <\/td>\n<\/tr>\n
430<\/td>\n17.5 Shared use of ZBSs by the EPU and STL <\/td>\n<\/tr>\n
436<\/td>\n17.6 EPU functionality associated with the ZBS count <\/td>\n<\/tr>\n
437<\/td>\n17.7 Programming considerations <\/td>\n<\/tr>\n
438<\/td>\n18. T1 TAP.7
18.1 Introduction <\/td>\n<\/tr>\n
439<\/td>\n18.2 Deployment
18.3 Capabilities <\/td>\n<\/tr>\n
440<\/td>\n18.4 Register and command portfolio <\/td>\n<\/tr>\n
444<\/td>\n18.5 Configurations <\/td>\n<\/tr>\n
445<\/td>\n18.6 Start-up behavior
18.7 Conditional Group Membership <\/td>\n<\/tr>\n
446<\/td>\n18.8 Test Reset <\/td>\n<\/tr>\n
448<\/td>\n18.9 Functional reset <\/td>\n<\/tr>\n
452<\/td>\n18.10 Power control <\/td>\n<\/tr>\n
473<\/td>\n18.11 RSU operation <\/td>\n<\/tr>\n
474<\/td>\n18.12 Programming considerations <\/td>\n<\/tr>\n
475<\/td>\n19. T2 TAP.7
19.1 Introduction <\/td>\n<\/tr>\n
477<\/td>\n19.2 Deployment
19.3 Capabilities <\/td>\n<\/tr>\n
478<\/td>\n19.4 Register and command portfolio <\/td>\n<\/tr>\n
480<\/td>\n19.5 Configurations
19.6 Start-up behavior <\/td>\n<\/tr>\n
481<\/td>\n19.7 Scan formats
19.8 STL Group Membership <\/td>\n<\/tr>\n
490<\/td>\n19.9 RSU operation <\/td>\n<\/tr>\n
491<\/td>\n19.10 Programming considerations <\/td>\n<\/tr>\n
492<\/td>\n20. T3 TAP.7
20.1 Introduction <\/td>\n<\/tr>\n
494<\/td>\n20.2 Deployment <\/td>\n<\/tr>\n
495<\/td>\n20.3 Capabilities
20.4 Register and command portfolio <\/td>\n<\/tr>\n
497<\/td>\n20.5 Configurations <\/td>\n<\/tr>\n
498<\/td>\n20.6 Start-up behavior
20.7 Scan formats <\/td>\n<\/tr>\n
499<\/td>\n20.8 TAP.7 Controller Address (TCA) <\/td>\n<\/tr>\n
501<\/td>\n20.9 Aliasing the TCA to a Controller ID <\/td>\n<\/tr>\n
509<\/td>\n20.10 Scan Selection Directives <\/td>\n<\/tr>\n
528<\/td>\n20.11 Scan Topology Training Sequence <\/td>\n<\/tr>\n
533<\/td>\n20.12 Managing STL Group Membership <\/td>\n<\/tr>\n
537<\/td>\n20.13 RSU operation <\/td>\n<\/tr>\n
538<\/td>\n20.14 Programming considerations <\/td>\n<\/tr>\n
539<\/td>\n21. Advanced concepts
21.1 Architecture <\/td>\n<\/tr>\n
540<\/td>\n21.2 Advanced capabilities <\/td>\n<\/tr>\n
542<\/td>\n21.3 Comparing the Standard and Advanced Protocols
21.4 APU functions <\/td>\n<\/tr>\n
547<\/td>\n21.5 APU interfaces <\/td>\n<\/tr>\n
550<\/td>\n21.6 APU function\/Operating State relationships <\/td>\n<\/tr>\n
554<\/td>\n21.7 TAPC state\/packet relationships <\/td>\n<\/tr>\n
559<\/td>\n21.8 User\u2019s and implementer\u2019s views of the Advanced Protocol <\/td>\n<\/tr>\n
560<\/td>\n21.9 An approach to implementing APU Operating State scheduling <\/td>\n<\/tr>\n
562<\/td>\n21.10 Structure of the clauses describing T4 and above TAP.7s <\/td>\n<\/tr>\n
564<\/td>\n22. APU Scan Packets
22.1 CPs
22.2 SPs <\/td>\n<\/tr>\n
569<\/td>\n22.3 SPs that advance the TAPC state <\/td>\n<\/tr>\n
570<\/td>\n22.4 TPs <\/td>\n<\/tr>\n
572<\/td>\n22.5 APU state diagram <\/td>\n<\/tr>\n
574<\/td>\n22.6 An approach to implementing packet scheduling <\/td>\n<\/tr>\n
576<\/td>\n23. T4 TAP.7
23.1 Introduction
23.2 Deployment <\/td>\n<\/tr>\n
577<\/td>\n23.3 Capabilities <\/td>\n<\/tr>\n
578<\/td>\n23.4 Register and command portfolio <\/td>\n<\/tr>\n
582<\/td>\n23.5 Configurations <\/td>\n<\/tr>\n
583<\/td>\n23.6 Start-up behavior <\/td>\n<\/tr>\n
584<\/td>\n23.7 Scan formats <\/td>\n<\/tr>\n
588<\/td>\n23.8 Configuration Faults <\/td>\n<\/tr>\n
589<\/td>\n23.9 Increasing STL performance <\/td>\n<\/tr>\n
592<\/td>\n23.10 Auxiliary Pin Function Control <\/td>\n<\/tr>\n
593<\/td>\n23.11 Sample Using Rising Edge <\/td>\n<\/tr>\n
594<\/td>\n23.12 System and EPU TMS signal values <\/td>\n<\/tr>\n
596<\/td>\n23.13 System and EPU TDI signal values <\/td>\n<\/tr>\n
598<\/td>\n23.14 RDY bit values <\/td>\n<\/tr>\n
600<\/td>\n23.15 TDO bit values <\/td>\n<\/tr>\n
601<\/td>\n23.16 Advanced Protocol effects on the EPU\/CLTAPC relationship
23.17 SSD detection <\/td>\n<\/tr>\n
602<\/td>\n23.18 Programming considerations
23.19 An approach to implementing a TAP.7 Controller with maximumperformance <\/td>\n<\/tr>\n
604<\/td>\n24. MScan Scan Format
24.1 Capabilities <\/td>\n<\/tr>\n
605<\/td>\n24.2 High-level operation <\/td>\n<\/tr>\n
606<\/td>\n24.3 Scan Packet content
24.4 Payload Element <\/td>\n<\/tr>\n
611<\/td>\n24.5 Delay Element <\/td>\n<\/tr>\n
614<\/td>\n24.6 Advancing the TAPC state
24.7 CID allocation <\/td>\n<\/tr>\n
616<\/td>\n24.8 Increasing STL performance with the MScan Scan Format
24.9 An approach to implementing the MScan Scan Format <\/td>\n<\/tr>\n
620<\/td>\n24.10 Where to find examples <\/td>\n<\/tr>\n
621<\/td>\n25. OScan Scan Formats
25.1 Capabilities <\/td>\n<\/tr>\n
622<\/td>\n25.2 High-level operation <\/td>\n<\/tr>\n
623<\/td>\n25.3 Scan Packet content <\/td>\n<\/tr>\n
624<\/td>\n25.4 Payload Element <\/td>\n<\/tr>\n
633<\/td>\n25.5 Delay Element <\/td>\n<\/tr>\n
634<\/td>\n25.6 Advancing the TAPC state <\/td>\n<\/tr>\n
636<\/td>\n25.7 CID allocation <\/td>\n<\/tr>\n
637<\/td>\n25.8 Increasing STL performance with OScan Scan Formats
25.9 An approach to implementing OScan Scan Formats <\/td>\n<\/tr>\n
641<\/td>\n25.10 Where to find examples <\/td>\n<\/tr>\n
642<\/td>\n26. SScan Scan Formats
26.1 Capabilities <\/td>\n<\/tr>\n
646<\/td>\n26.2 High-level operation <\/td>\n<\/tr>\n
651<\/td>\n26.3 Scan Packet content <\/td>\n<\/tr>\n
653<\/td>\n26.4 Header Element <\/td>\n<\/tr>\n
654<\/td>\n26.5 Payload Element <\/td>\n<\/tr>\n
669<\/td>\n26.6 Delay Element <\/td>\n<\/tr>\n
670<\/td>\n26.7 Packet sequences and factors influencing them <\/td>\n<\/tr>\n
673<\/td>\n26.8 Advancing the TAPC state <\/td>\n<\/tr>\n
678<\/td>\n26.9 CID allocation <\/td>\n<\/tr>\n
679<\/td>\n26.10 Increasing STL performance with SScan Scan Formats
26.11 An approach to implementing SScan Scan Formats <\/td>\n<\/tr>\n
686<\/td>\n26.12 Where to find examples <\/td>\n<\/tr>\n
687<\/td>\n27. T5 TAP.7
27.1 Introduction <\/td>\n<\/tr>\n
688<\/td>\n27.2 Deployment <\/td>\n<\/tr>\n
689<\/td>\n27.3 Capabilities
27.4 Register and command portfolio <\/td>\n<\/tr>\n
696<\/td>\n27.5 Configurations <\/td>\n<\/tr>\n
698<\/td>\n27.6 Start-up behavior
27.7 Configuration Faults <\/td>\n<\/tr>\n
699<\/td>\n27.8 Enabling transport <\/td>\n<\/tr>\n
700<\/td>\n27.9 Transport Packet composition <\/td>\n<\/tr>\n
701<\/td>\n27.10 Directive Elements <\/td>\n<\/tr>\n
712<\/td>\n27.11 Register Elements <\/td>\n<\/tr>\n
713<\/td>\n27.12 Data Elements <\/td>\n<\/tr>\n
716<\/td>\n27.13 Selection of control and data targets <\/td>\n<\/tr>\n
717<\/td>\n27.14 Data Channel Client functions <\/td>\n<\/tr>\n
719<\/td>\n27.15 Partitioning of the Transport Control Function <\/td>\n<\/tr>\n
722<\/td>\n27.16 Programming considerations <\/td>\n<\/tr>\n
725<\/td>\n28. Transport operation and interfaces
28.1 Introduction
28.2 TAP interface <\/td>\n<\/tr>\n
736<\/td>\n28.3 Transport State Machine <\/td>\n<\/tr>\n
743<\/td>\n28.4 PDCx\/DCC interface <\/td>\n<\/tr>\n
750<\/td>\n28.5 Five-bit directives <\/td>\n<\/tr>\n
753<\/td>\n28.6 Eight-bit directives <\/td>\n<\/tr>\n
754<\/td>\n28.7 12-bit directives <\/td>\n<\/tr>\n
757<\/td>\n28.8 DCC interface operation <\/td>\n<\/tr>\n
759<\/td>\n28.9 An approach to implementing the Transport Function <\/td>\n<\/tr>\n
774<\/td>\n29. Test concepts
29.1 Introduction
29.2 Interoperability <\/td>\n<\/tr>\n
775<\/td>\n29.3 Construction of the unit under test
29.4 Background (IEEE 1149.1 paradigm) <\/td>\n<\/tr>\n
777<\/td>\n29.5 Implications for test applications arising from this standard <\/td>\n<\/tr>\n
778<\/td>\n29.6 Test example\u2014a narrative <\/td>\n<\/tr>\n
779<\/td>\n29.7 Describing the unit under test <\/td>\n<\/tr>\n
780<\/td>\n29.8 Documentation model <\/td>\n<\/tr>\n
781<\/td>\n29.9 Considerations for large-system applications <\/td>\n<\/tr>\n
783<\/td>\n30. Documenting IEEE 1149.7 test endpoints (BSDL.7)
30.1 Introduction <\/td>\n<\/tr>\n
784<\/td>\n30.2 Conventions
30.3 Purpose of BSDL.7
30.4 Scope of BSDL.7 <\/td>\n<\/tr>\n
785<\/td>\n30.5 Expectations of a BSDL.7 parser
30.6 Relationship of BSDL.7 to BSDL.1 <\/td>\n<\/tr>\n
786<\/td>\n30.7 Lexical elements of BSDL.7
30.8 BSDL.7 reserved words <\/td>\n<\/tr>\n
787<\/td>\n30.9 Components of a BSDL.7 description
30.10 The entity description (BSDL.7) <\/td>\n<\/tr>\n
799<\/td>\n30.11 The Standard VHDL Package STD_1149_7_2009 <\/td>\n<\/tr>\n
800<\/td>\n30.12 A typical application of BSDL.7 <\/td>\n<\/tr>\n
803<\/td>\n31. Documenting IEEE 1149.7 test modules (HSDL.7)
31.1 Introduction
31.2 Conventions <\/td>\n<\/tr>\n
804<\/td>\n31.3 Purpose of HSDL.7
31.4 Scope of HSDL.7 <\/td>\n<\/tr>\n
805<\/td>\n31.5 Expectations of an HSDL.7 parser
31.6 Relationship of HSDL.7 to BSDL.7 (and BSDL.1) <\/td>\n<\/tr>\n
806<\/td>\n31.7 Lexical elements of HSDL.7
31.8 HSDL.7 reserved words
31.9 Components of an HSDL.7 description <\/td>\n<\/tr>\n
807<\/td>\n31.10 The entity description (HSDL.7) <\/td>\n<\/tr>\n
819<\/td>\n31.11 The Standard VHDL Package STD_1149_7_2009_module
31.12 Applications of HSDL.7 <\/td>\n<\/tr>\n
827<\/td>\nAnnex A (informative) IEEE 1149.1 reference material <\/td>\n<\/tr>\n
830<\/td>\nAnnex B (informative) Scan examples in timing diagram form <\/td>\n<\/tr>\n
857<\/td>\nAnnex C (informative) Scan examples in tabular form <\/td>\n<\/tr>\n
899<\/td>\nAnnex D (informative) Programming considerations <\/td>\n<\/tr>\n
928<\/td>\nAnnex E (informative) Recommended electrical characteristics <\/td>\n<\/tr>\n
929<\/td>\nAnnex F (informative) Connectivity\/electrical recommendations <\/td>\n<\/tr>\n
1014<\/td>\nAnnex G (informative) Utilizing SScan Scan Formats <\/td>\n<\/tr>\n
1018<\/td>\nAnnex H (informative) The RTCK signal <\/td>\n<\/tr>\n
1026<\/td>\nAnnex I (informative) Bibliography <\/td>\n<\/tr>\n
1027<\/td>\nIndex
1-C <\/td>\n<\/tr>\n
1028<\/td>\nC <\/td>\n<\/tr>\n
1029<\/td>\nC-D <\/td>\n<\/tr>\n
1030<\/td>\nD-G <\/td>\n<\/tr>\n
1031<\/td>\nG-N <\/td>\n<\/tr>\n
1032<\/td>\nO-P <\/td>\n<\/tr>\n
1033<\/td>\nP-R <\/td>\n<\/tr>\n
1034<\/td>\nR-S <\/td>\n<\/tr>\n
1035<\/td>\nS-T <\/td>\n<\/tr>\n
1036<\/td>\nT <\/td>\n<\/tr>\n
1037<\/td>\nT-Z <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard for Reduced-Pin and Enhanced-Functionality Test Access Port and Boundary-Scan Architecture<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n2009<\/td>\n1037<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":399620,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-399615","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/399615","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/399620"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=399615"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=399615"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=399615"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}